• DocumentCode
    497967
  • Title

    A dual-channel 10b 80MS/s pipeline ADC with 0.16mm2 area in 65nm CMOS

  • Author

    Yu, Xinyu ; Lin, Fang ; Li, Kevin ; Ranganathan, Sumant ; Kwan, Tom

  • Author_Institution
    Broadcom Corporation, 3151 Zanker Road, San Jose, CA, USA
  • fYear
    2009
  • fDate
    16-18 June 2009
  • Firstpage
    272
  • Lastpage
    273
  • Abstract
    A dual-channel 10b 80MS/s low-power and area-efficient pipeline ADC is presented. Area and power savings are realized by merging the track and hold amplifier (THA) and the 1st-stage multiplying digital-to-analog converter (MDAC), double-sampling the 2nd-stage MDAC and using a 1b sub-range in 4b sub-ADC. It achieves an ENOB of 8.65b with 20.1-MHz input. Including on-chip reference buffers, power and area consumption are 11.2mW and 0.08mm2 per channel respectively.
  • Keywords
    Capacitors; Circuit noise; Delay; Merging; Pipelines; Power amplifiers; Sampling methods; Switches; Throughput; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2009 Symposium on
  • Conference_Location
    Kyoto, Japan
  • Print_ISBN
    978-1-4244-3307-0
  • Electronic_ISBN
    978-4-86348-001-8
  • Type

    conf

  • Filename
    5205318
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=497967