DocumentCode
497974
Title
A 200Mbps+ 2.14nJ/b digital baseband multi processor system-on-chip for SDRs
Author
Derudder, V. ; Bougard, B. ; Couvreur, A. ; Dewilde, A. ; Dupont, S. ; Folens, L. ; Hollevoet, L. ; Naessens, F. ; Novo, D. ; Raghavan, P. ; Schuster, T. ; Stinkens, K. ; Weijers, J.-W. ; Van der Perre, L.
Author_Institution
IMEC vzw, Kapeldreef 75, B3001 Leuven, Belgium
fYear
2009
fDate
16-18 June 2009
Firstpage
292
Lastpage
293
Abstract
This paper describes the implementation of an energy-efficient digital SDR baseband platform. The multi processor system-on-chip (MPSOC) is implemented in 90nm CMOS technology and occupies 32mm2. It incorporates all digital signal processing required by the physical layer of the WiFi(802.11n), WiMax(802.16e), mobile TV and 3GPP-LTE standards. The heterogeneous architecture with hierarchical wake-up achieves 5mW idle time power, is capable of delivering a net data rate in excess of 200Mbps and consumes 231mW during 108Mbps WLAN 2×2 MIMO Rx, achieving 2.14nJ/b energy efficiency.
Keywords
Baseband; CMOS process; CMOS technology; Digital signal processing; Energy efficiency; Mobile TV; Physical layer; System-on-a-chip; WiMAX; Wireless LAN; software-defined radio (SDR); wireless communication;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2009 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
978-1-4244-3307-0
Electronic_ISBN
978-4-86348-001-8
Type
conf
Filename
5205326
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