• DocumentCode
    497975
  • Title

    Multi-stacked 1G cell/layer Pipe-shaped BiCS flash memory

  • Author

    Maeda, Takashi ; Itagaki, Kiyotaro ; Hishida, Tomoo ; Katsumata, Ryota ; Kito, Masaru ; Fukuzumi, Yoshiaki ; Kido, Masaru ; Tanaka, Hiroyasu ; Komori, Yosuke ; Ishiduki, Megumi ; Matsunami, Junya ; Fujiwara, Tomoko ; Aochi, Hideaki ; Iwata, Yoshihisa ; Wa

  • Author_Institution
    Center for Semiconductor Research & Development, Toshiba Corporation, Semiconductor Company, 2-5-1 Kasama, Sakae-ku, Yokohama, Kanagawa, 247-8585, Japan
  • fYear
    2009
  • fDate
    16-18 June 2009
  • Firstpage
    22
  • Lastpage
    23
  • Abstract
    A three-dimensional 16 stacked 1G cell/layer Pipe-shaped Bit-Cost Scalable (P-BiCS) flash memory test chip with 60nm technology has been developed. The effective 1-bit cell size is 0.00082 um2. This paper describes the branched control gate configuration and the new erase operation which are suitable for P-BiCS flash memory. P-BiCS flash memory is one of the most promising candidates for realizing the future T-bit storage device.
  • Keywords
    Costs; Decoding; Driver circuits; Flash memory; Leakage current; Semiconductor device testing; Silicon; Stacking; Substrates; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2009 Symposium on
  • Conference_Location
    Kyoto, Japan
  • Print_ISBN
    978-1-4244-3307-0
  • Electronic_ISBN
    978-4-86348-001-8
  • Type

    conf

  • Filename
    5205327
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=497975