DocumentCode
497976
Title
Dynamic Vpass ISPP scheme and optimized erase Vth control for high program inhibition in MLC NAND flash memories
Author
Park, Ki-Tae ; Kang, Myounggon ; Hwang, Soonwook ; Song, Youngsun ; Lee, Jaewook ; Joo, Hansung ; Oh, Hyun-Sil ; Kim, Jae-ho ; Lee, Yeong-Taek ; Kim, Changhyun ; Lee, Wonseong
Author_Institution
Memory R&D Center, Memory Business, Samsung Electronics Co., Ltd., San #14, Banwol-Dong, Hwasung-City, Gyeonggi-Do, Korea, 445-701
fYear
2009
fDate
16-18 June 2009
Firstpage
24
Lastpage
25
Abstract
In this paper, dynamic Vpass ISPP schemes and optimizing Vth of erase cells are presented for achieving high program inhibition of sub-40nm MLC NAND flash and beyond. Compared to conventional method, over 40% program failure reduction after 30k P/E cycling was achieved in the proposed scheme. By optimizing erase Vth and its distribution using ISPP-after-erase, about 2 times better Vpass window margin was obtained in 40nm-node MLC NAND test chip.
Keywords
Acceleration; Degradation; Doping; Electrons; Research and development; Semiconductor device measurement; Space vector pulse width modulation; Stress; Testing; Voltage control;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2009 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
978-1-4244-3307-0
Electronic_ISBN
978-4-86348-001-8
Type
conf
Filename
5205328
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