Title :
A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process
Author :
Liu, Chun-Cheng ; Chang, Soon-Jyh ; Huang, Guan-Ying ; Lin, Yin-Zu
Author_Institution :
Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan
Abstract :
This paper reports a 10-bit 50MS/s SAR ADC with a set-and-down capacitor switching method. Compared to the conventional method, the average switching energy is reduced about 81%. At 50MS/s and 1.2V supply, the ADC consumes 0.92mW and achieves an SNDR of 52.78dB, resulting in an FOM of 52fJ/Conversion-step. Fabricated in a 0.13μm 1P8M CMOS technology, the ADC only occupies 0.075mm2 active area.
Keywords :
CMOS process; CMOS technology; Circuits; Energy consumption; Frequency; Power dissipation; Registers; Switched capacitor networks; Switches; Voltage;
Conference_Titel :
VLSI Circuits, 2009 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
978-1-4244-3307-0
Electronic_ISBN :
978-4-86348-001-8
