• DocumentCode
    497989
  • Title

    A 1.3μW 0.6V 8.7-ENOB successive approximation ADC in a 0.18μm CMOS

  • Author

    Lee, Seon-Kyoo ; Park, Seung-Jin ; Suh, Yunjae ; Park, Hong-June ; Sim, Jae-Yoon

  • Author_Institution
    Pohang University of Science and Technology(POSTECH), San 31, Hyojadong, Namgu, Kyungbuk, 790-784, Korea
  • fYear
    2009
  • fDate
    16-18 June 2009
  • Firstpage
    242
  • Lastpage
    243
  • Abstract
    A 100KS/s, 1.3μW, 8.7-ENOB successive approximation ADC is proposed with a time-domain comparator which uses a highly digital differential VCDL architecture. Without any reference voltage, the capacitor DAC performs a rail-to-rail conversion range. The ADC, implemented in a standard 0.18μm CMOS, shows a FoM of 31fJ/conversion-step with a single supply voltage of 0.6V.
  • Keywords
    Analog circuits; CMOS technology; Capacitors; Delay; Digital circuits; Energy consumption; MOS devices; Sampling methods; Time domain analysis; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2009 Symposium on
  • Conference_Location
    Kyoto, Japan
  • Print_ISBN
    978-1-4244-3307-0
  • Electronic_ISBN
    978-4-86348-001-8
  • Type

    conf

  • Filename
    5205346
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=497989