DocumentCode
498005
Title
A 2 × 22Gb/s SFI5.2 CDR/deserializer in 65nm CMOS technology
Author
Nedovic, Nikola ; Parikh, Samir ; Kristensson, Anders ; Tzartzanis, Nestoras ; Walker, William ; Reddy, Subodh ; Tamura, Hirotaka ; McLeod, Scott ; Yamamoto, Takuji ; Doi, Yoshiyasu ; Ogawa, Junji ; Kibune, Masaya ; Shibasaki, Takayuki ; Hamada, Takayuki
Author_Institution
Fujitsu Laboratories of America, 1240 E Arques Ave. M/S 345, Sunnyvale, CA 94085, USA
fYear
2009
fDate
16-18 June 2009
Firstpage
10
Lastpage
11
Abstract
A CDR/deserializer IC is designed in 65nm triple-well CMOS, dissipates 1.3W, receives two 20.6–22.3Gb/s (DQPSK) data channels, and outputs 4⊲1 × 10.65−11.3Gb/s SFI5.2 data and deskew channel. The deserializer comprises two limiting amplifiers, a 2 × 20G to 16 × 2.5G CDR/DEMUX, a synchronizing FIFO, SFI5.2 deskew channel generator, and a 5×2.5 to 10G MUX. It also includes a 5GHz PLL, a a 2.5Gb/s PRBS and BERT, a temperature sensor, and an I2C bus.
Keywords
Bit error rate; CMOS integrated circuits; CMOS technology; Clocks; Laboratories; Logic testing; Optical amplifiers; Optical fiber communication; Phase locked loops; Temperature sensors; CDR; DQPSK; SFI5.2;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2009 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
978-1-4244-3307-0
Electronic_ISBN
978-4-86348-001-8
Type
conf
Filename
5205366
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