Adaptation of CDR and full scale range of ADC-based SerDes receiver

An adaptation strategy of CDR phase and ADC full scale range (FSR) for an ADC-based SerDes receiver is proposed and demonstrated in a 65-nm test chip. With the clock phase adapted by a metric based on the bit-error-rate (BER), the silicon operates over a wider range of channels or link settings compared to a typical Mueller-Müller CDR algorithm. The strategy also adapts the ADC FSR. The optimal setting achieves an equivalent resolution with fewer ADC comparators compared to an ADC that digitizes the entire inp ut signal.