DocumentCode
498014
Title
A 19Gb/s 38mW 1-tap speculative DFE receiver in 90nm CMOS
Author
Turker, Didem Z. ; Rylyakov, Alexander ; Friedman, Daniel ; Gowda, Sudhir ; Sánchez-Sinencio, Edgar
Author_Institution
Texas A&M University, College Station, USA
fYear
2009
fDate
16-18 June 2009
Firstpage
216
Lastpage
217
Abstract
A half-rate sampling 1-tap speculative DFE in 90nm CMOS operates at speeds up to 23Gb/s through ISI cancellation in the input latch of the receiver. The decision threshold of the latch is varied over a wide range without loss of bandwidth or sensitivity. For a 19Gb/s PRBS7 data stream sent over a 10-inch channel (-11dB at 9.5GHz) that results in a closed post-channel input eye, the DFE operates with a BER of 10−8 for 9% UI horizontal eye opening at its output (BER ≪ 10−13 at the eye center), consuming 38mW from a 1V supply.
Keywords
Adders; Bandwidth; Bit error rate; Circuits; Clocks; Decision feedback equalizers; Intersymbol interference; Latches; Quadratic programming; Sampling methods; DFE; Half-rate sampling; ISI; speculation;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2009 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
978-1-4244-3307-0
Electronic_ISBN
978-4-86348-001-8
Type
conf
Filename
5205375
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