• DocumentCode
    498015
  • Title

    A 40Gb/s decision feedback equalizer using back-gate feedback technique

  • Author

    Hsieh, Chang-Lin ; Liu, Shen-Iuan

  • Author_Institution
    Graduate Institute of Electronics Engineering & Department of Electrical Engineering, National Taiwan University, Taipei, 10617, R. O. C.
  • fYear
    2009
  • fDate
    16-18 June 2009
  • Firstpage
    218
  • Lastpage
    219
  • Abstract
    A one-tap 40Gb/s decision feedback equalizer (DFE) has been fabricated in 65nm CMOS technology. The proposed DFE adopts an adder by using the back-gate feedback technique to achieve a high operation speed. The measured bit error rate is below 10−11for a 27−1 PRBS of 40Gb/s. The power dissipation is 45mW from 1.2V supply without output buffers.
  • Keywords
    Adders; Breakdown voltage; CMOS technology; Decision feedback equalizers; Energy consumption; Equations; Feedback amplifiers; Parasitic capacitance; Power dissipation; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2009 Symposium on
  • Conference_Location
    Kyoto, Japan
  • Print_ISBN
    978-1-4244-3307-0
  • Electronic_ISBN
    978-4-86348-001-8
  • Type

    conf

  • Filename
    5205376
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=498015