DocumentCode :
498020
Title :
A 45nm 24MB on-die L3 cache for the 8-core multi-threaded Xeon® Processor
Author :
Chang, Jonathan ; Chen, Szu-Liang ; Chen, Wei ; Chiu, Siufu ; Faber, Robert ; Ganesan, Raghuraman ; Grgek, Marijana ; Lukka, Venkata ; Mar, Wei Wing ; Vash, James ; Rusu, Stefan ; Zhang, Kevin
Author_Institution :
Intel Corporation, 2200 Mission College Blvd. (SC12-408), Santa Clara, CA 95052, USA
fYear :
2009
fDate :
16-18 June 2009
Firstpage :
152
Lastpage :
153
Abstract :
The 24-way set associative 24MB 8-ported L3 cache for the 8-core Xeon® Processor uses 0.3816 µm02 cell in a 45nm high-K dielectric metal gate technology 9-copper layers. It is protected by double-error correction/triple-error detection ECC. The basic building block is designed to support completely different floorplan styles on 2 processors with large L3 cache. Off die fuse storage enables high resolution repair coverage.
Keywords :
Copper; Delay; Educational institutions; Error correction codes; Frequency; Fuses; High-K gate dielectrics; Manufacturing processes; Protection; Sleep;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 2009 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
978-1-4244-3307-0
Electronic_ISBN :
978-4-86348-001-8
Type :
conf
Filename :
5205386
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=498020
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