DocumentCode :
498023
Title :
A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist
Author :
Yabuuchi, M. ; Nii, K. ; Tsukamoto, Y. ; Ohbayashi, S. ; Nakase, Y. ; Shinohara, H.
Author_Institution :
Renesas Technology Corp., 4-1, Mizuhara, Itami, Hyogo, Japan
fYear :
2009
fDate :
16-18 June 2009
Firstpage :
158
Lastpage :
159
Abstract :
We propose a new design solution for embedded SRAM macros with cross point 8T-SRAM for low operating voltage and power. A negative bias technique for VSS and bitline (BL) enables us to achieve not only low power and high access speed, but also the large cell stability and write ability. Using 45-nm CMOS technology, we fabricated the SRAM macro based on our proposal and confirmed that the 1Mbit-SRAM successfully operated at 0.6V. The active power is reduced by 66%, compared to the conventional 6T-SRAM.
Keywords :
CMOS technology; Capacitance; Circuit stability; Dynamic voltage scaling; Energy consumption; Frequency; Low voltage; Proposals; Random access memory; Variable structure systems; 45nm; 8T; DVFS; SRAM; assist circuit; cross point;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 2009 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
978-1-4244-3307-0
Electronic_ISBN :
978-4-86348-001-8
Type :
conf
Filename :
5205389
Link To Document :
بازگشت