A bandwidth tracking technique for a 65nm CMOS digital phase-locked loop

This paper presents a technique to achieve the bandwidthtracking ability of digital PLLs used for clock generation in large digital systems. The technique uses replica delay cells in the DCO and the PD for ≫100× range of operating frequency. Measurement results show a near constant damping factor and the tracking of the loop bandwidth to reference frequency over 2× of core oscillation frequencies (2.5GHz–5.0GHz) and reference frequencies from 19.5MHz to 312MHz without calibration.