A versatile generator of instruction set simulators and disassemblers

Instruction-set simulators (ISS) are more and more used in design space exploration and functional software testing. Furthermore, cycle-accurate simulators are often made of a functional coupled to a timing simulator. Research about ISS generators is not new but most often addresses only simple instruction sets (i.e. RISC). This paper describes techniques to ease the description of complex Instruction-Set Architectures and to increase simulation speed. They are integrated in a tool which generates libraries containing functions to disassemble (useful for testing), decode and simulate many different architectures like RISC, CISC, VLIW and is able to deal with variable-length instructions. We successfully generated and used ARM/thumb, HCS 12X, Tricore, Sharc, PPC simulators and experiments have been made on the x86 architecture.