Layout-Versus-Schematic Verification for Superconductive Integrated Circuits

Thorough layout verification of superconducting integrated circuits goes beyond design rule checking and parameter value extraction. The former is used to verify adherence to process design rules, and the latter to determine component element values. Still, neither gives much warning against subtle layout errors that result in unintended parasitic elements, or a layout that does not reflect the original circuit topology. A specialized implementation for Cadence Virtuoso allows layout-versus-schematic (LVS) verification, but is limited to commercial software and in terms of usefulness. Parameter extraction software such as InductEx require the circuit topology to be provided as a netlist, and element values are extracted for this topology even if a mistake in the layout or the netlist results in a model mismatch. Here we present a free-standing LVS verification toolkit for superconductive integrated circuits, and discuss its implementation. It comprises layout-to-schematic conversion that creates a first-pass netlist, netlist simplification, netlist and schematic visualization for user feedback, and netlist comparison to determine if a layout agrees with an input schematic. We show results for gate-level layouts and how it is used with InductEx to perform automated parameter extraction for layout verification. We conclude that this work makes layout verification more efficient and minimizes layout mistakes.