DocumentCode
500777
Title
Handling complexities in modern large-scale mixed-size placement
Author
Yan, Jackey Z. ; Viswanathan, Natarajan ; Chu, Chris
Author_Institution
Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA
fYear
2009
fDate
26-31 July 2009
Firstpage
436
Lastpage
441
Abstract
In this paper, we propose an effective algorithm flow to handle large-scale mixed-size placement. The basic idea is to use floorplanning to guide the placement of objects at the global level. The flow consists of four steps: (1) The objects in the original netlist are clustered into blocks; (2) Floorplanning is performed on the blocks; (3) The blocks are shifted within the chip region to further optimize the wirelength; (4) With big macro locations fixed, incremental placement is applied to place the remaining objects. There are several advantages of handling placement at the global level with a floorplanning technique. First, the problem size can be significantly reduced. Second, exact HPWL can be minimized. Third, precise object distribution can be achieved so that legalization only needs to handle minor overlaps among small objects in a block. Fourth, rotation and various placement constraints on macros can be handled. To demonstrate the effectiveness of this new flow, we implement a high-quality floorplan-guided placer called FLOP. We also construct the Modern Mixed-Size (MMS) placement benchmarks which can effectively represent the complexities of modern mixed-size designs and the challenges faced by modern mixed-size placers. Compared with state-of-the-art mixed-size placers and leading macro placers, experimental results show that FLOP achieves the best wirelength, and easily obtains legal solutions on all circuits.
Keywords
circuit layout CAD; FLOP; algorithm flow; floorplanning technique; handling placement; high quality floorplan-guided placer; incremental placement; large-scale mixed-size placement; macro placer; modern mixed-size design; modern mixed-size placement; modern mixed-size placer; object distribution; Algorithm design and analysis; Circuits; Clustering algorithms; Large-scale systems; Law; Legal factors; Partitioning algorithms; Permission; Routing; Very large scale integration; Floorplanning; Incremental Placement; Mixed-size Design;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE
Conference_Location
San Francisco, CA
ISSN
0738-100X
Print_ISBN
978-1-6055-8497-3
Type
conf
Filename
5227031
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