Untwist your brain - Efficient debugging and diagnosis of complex assertions

Assertions are recognized in the industry to be a major improvement in functional RTL verification flows. Today´s standard assertion languages, such as SVA and PSL are very expressive, capable of describing sophisticated temporal design behavior at different abstraction levels. Nevertheless, most assertion users stick to writing simple assertions because of the intricacy and effort required to debug complex assertions: one of the major bottlenecks in assertion based verification. We present debugging and diagnosis techniques that automatically identify those parts of an assertion that cause the assertion to fail for a given design and that provide additional automation to efficiently identify the root cause of the failure. These techniques enable major effort savings when working with complex assertions, allowing engineers to use the full capabilities of assertion languages. This enables further productivity and quality improvements in functional verification by lifting mainstream assertion usage to higher abstraction levels such as efficient capture and verification of highlevel design features, operations, and transactions. Advanced debugging automation is key for this progress, solving a problem that many designers and verification engineers face in their daily work.