Hardware authentication leveraging performance limits in detailed simulations and emulations

This paper proposes a novel approach to check the authenticity of hardware based on the inevitable performance gap between real hardware and simulations or emulations that impersonate it. More specifically, we demonstrate that each processor design can be authenticated by requiring a checksum incorporating internals of complex microarchitectural mechanisms to be computed within a time limit; this checksum is different for each processor model and only authentic secure hardware can obtain the checksum fast enough. This new authentication approach provides attractive solutions to privacy, scaling, and security issues of traditional approaches that otherwise rely only on certificates. Architectural simulations and an RTL implementation show that the proposed approach is viable with very low hardware overheads.