• DocumentCode
    500903
  • Title

    GPU-based parallelization for fast circuit optimization

  • Author

    Liu, Yifang ; Hu, Jiang

  • Author_Institution
    Dept. of ECE, Texas A&M Univ., College Station, TX, USA
  • fYear
    2009
  • fDate
    26-31 July 2009
  • Firstpage
    943
  • Lastpage
    946
  • Abstract
    The progress of GPU (graphics processing unit) technology opens a new avenue for boosting computing power. This work is an attempt to exploit GPU for accelerating VLSI circuit optimization. We propose GPU-based parallel computing techniques and apply them on simultaneous gate sizing and threshold voltage assignment, which is often employed in practice for performance and power optimization. These techniques are aimed to fully utilize the benefits of GPU through efficient task scheduling and memory organization. Compared to conventional sequential computation, our techniques can provide up to 56times speedup without any sacrifice on solution quality.
  • Keywords
    VLSI; circuit CAD; circuit optimisation; computer graphics; coprocessors; integrated circuit design; parallel processing; GPU-based parallel computing; GPU-based parallelization; VLSI circuit optimization; gate sizing; graphics processing unit; Algorithm design and analysis; Boosting; Circuit optimization; Combinational circuits; Concurrent computing; Graphics; Parallel processing; Processor scheduling; Threshold voltage; Very large scale integration; GPU; VLSI circuit optimization; parallel computing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE
  • Conference_Location
    San Francisco, CA
  • ISSN
    0738-100X
  • Print_ISBN
    978-1-6055-8497-3
  • Type

    conf

  • Filename
    5227161