DocumentCode
500934
Title
Design perspectives on 22nm CMOS and beyond
Author
Borkar, Shekhar
Author_Institution
Intel Corp., Hillsboro, OR, USA
fYear
2009
fDate
26-31 July 2009
Firstpage
93
Lastpage
94
Abstract
This paper presents technology and economic challenges posed by 22 nm CMOS and beyond, and how they can be addressed by advances in design technology, validation, and testing, to exploit the benefits of scaling we have enjoyed over the decades.
Keywords
CMOS integrated circuits; integrated circuit design; integrated circuit testing; nanotechnology; CMOS; design perspective; design technology; testing; validation; CMOS technology; Costs; Delay; Dynamic voltage scaling; Lithography; Manufacturing; Power generation economics; Power system reliability; Testing; Threshold voltage; CMOS; Nano; Power; Variability;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE
Conference_Location
San Francisco, CA
ISSN
0738-100X
Print_ISBN
978-1-6055-8497-3
Type
conf
Filename
5227192
Link To Document