Impact of pin configuration in IV characterization on ESD failure analysis

Author

Gong, Excimer ; Qin, Tim ; Guo, Annie ; Qiang Guo ; Chien, Wei-Ting Kary

Author_Institution

Anal. Lab., Semicond. Manuf. Int. (Shanghai) Corp., Shanghai, China

fYear

2009

fDate

6-10 July 2009

Firstpage

200

Lastpage

203

Abstract

During ESD (electro-static discharge) tests, IV curves are measured before and after ESD stress to judge the ESD protection circuit performance. In this paper, we report that the judgment in this way may be misleading if the pin configuration of the power supply pins or control pins are not well defined. Experiments & analysis are illustrated on configurations of: 1) Vss and Vdd pins, 2) Vdd pins from multiple power domains. We recommended that industry standards define the procedure on IV curve measurement and pin configurations as guidelines for ESD tests.

Keywords

electrostatic discharge; failure analysis; integrated circuit reliability; integrated circuit testing; ESD failure analysis; ESD protection circuit; IV curves measurement; control pins; electro-static discharge testing; pin configuration; power supply pins; Circuit optimization; Circuit testing; Electricity supply industry; Electrostatic discharge; Failure analysis; Pins; Power supplies; Protection; Stress measurement; Variable structure systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the

Conference_Location

Suzhou, Jiangsu

ISSN

1946-1542

Print_ISBN

978-1-4244-3911-9

Electronic_ISBN

1946-1542

Type

conf

DOI

10.1109/IPFA.2009.5232670

Filename

5232670