Automatic layout based verification of electrostatic discharge paths

This work describes an ESD path verification methodology based on layout parasitic extraction. This approach was implemented in Cadence DFII. It provides information about the preferred ESD path between two pads and estimates the peak pad to pad voltage. The path can also be overlaid on the layout view. The methodology was applied to a 0.5 um BiCMOS design to improve its ESD robustness. In that case, weak ESD paths overlooked during conventional design reviews were identified and corrected. The ESD robustness improved from 1.0 kV to 2.5 kV and 100 V to 250 V for HBM and MM respectively.