DocumentCode :
501910
Title :
Experimental analysis and electro-thermal simulation of low- and high-voltage ESD protection bipolar devices in a Silicon-On-Insulator Bipolar-CMOS-DMOS technology
Author :
Depetro, R. ; Mignoli, F. ; Andreini, A. ; Contiero, C. ; Meneghesso, G. ; Zanoni, E.
Author_Institution :
Dedicated Products Group, ST-Microelectron., Milan, Italy
fYear :
2001
fDate :
11-13 Sept. 2001
Firstpage :
101
Lastpage :
108
Abstract :
We present the results of extensive characterization of fully isolated SOI NPN bipolar protection devices by means of both 2D simulations, DC and TLP measurements, and HBM/TLP ESD stress tests. Excellent agreement between measured and simulated quasistatic and pulsed I-V characteristics of the protection structures has been obtained. We also confirm the usefulness of 2D/3D device simulations for ESD optimization.
Keywords :
CMOS integrated circuits; circuit optimisation; electrostatic discharge; silicon-on-insulator; 2D simulations; ESD optimization; NPN bipolar protection devices; bipolar devices; bipolar-CMOS-DMOS technology; electro-thermal simulation; high-voltage ESD protection; low-voltage ESD protection; silicon-on-insulator; Analytical models; CMOS technology; Dielectrics; Doping; Electrostatic discharge; Protection; Pulse measurements; Silicon on insulator technology; Testing; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 2001. EOS/ESD '01.
Conference_Location :
Portland, OR
Print_ISBN :
978-1-5853-7039-9
Electronic_ISBN :
978-1-5853-7039-9
Type :
conf
Filename :
5254983
Link To Document :
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