DocumentCode
501920
Title
5-V tolerant fail-safe ESD solutions for 0.18µm logic CMOS process
Author
Kunz, Keith ; Duvvury, Charvaka ; Shichijo, Hisashi
Author_Institution
Texas Instrum., Inc., Dallas, TX, USA
fYear
2001
fDate
11-13 Sept. 2001
Firstpage
12
Lastpage
21
Abstract
Failsafe, high voltage tolerant, low capacitive ESD solutions are implemented in a 0.18 mum dual- gate advanced CMOS technology. This technology features a drain-extended transistor with BVdss of 13 V. Protection of drain extended transistors that allow up to 7V drain operating voltage using 70Aringring oxide is investigated with the integration of a special ldquoself-alignedrdquo STI-blocked SCR structure. Excellent HBM and CDM performance for the I/O applications with this approach are demonstrated.
Keywords
CMOS logic circuits; electrostatic discharge; STI-blocked SCR structure; drain-extended transistor; logic CMOS process; low capacitive ESD solution; size 0.18 micron; voltage 13 V; voltage 7 V; CMOS logic circuits; CMOS process; CMOS technology; Capacitance; Electrostatic discharge; Low voltage; Protection; Rails; Thyristors; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium, 2001. EOS/ESD '01.
Conference_Location
Portland, OR
Print_ISBN
978-1-5853-7039-9
Electronic_ISBN
978-1-5853-7039-9
Type
conf
Filename
5254993
Link To Document