Light-Load Efficiency Improvement in Buck-Derived Single-Stage Single-Switch PFC Converters

Single-stage single-switch ac/dc converters with power factor correction (PFC) generally have higher power losses under a light-load condition, as compared to that of the two-stage approach, due to the sharing of a common power transistor such that the PFC stage cannot be switched OFF separately to save power losses. This letter addresses this problem by using a buck topology for the PFC stage of the single-stage single-switch converters as it can be completely turned OFF by operating the converter only near the zero crossing of the input voltage, due to the presence of the dead angle of input current. Hence, the switching and conduction losses to the transistor and diodes, and passive devices are reduced. Also, further improvement is made by finding the best combination of dc-bus capacitor charging time and discharging time to achieve the lowest power loss. A recently proposed converter topology which combines a buck PFC cell with a buck-boost dc/dc cell is used as an example. Experimental results are reported and confirmed that the proposed light-load power loss reduction scheme on the converter can improve power stage efficiency by up to 7% at 1 W of output power as compared to that without the proposed scheme.