Optimization of Integrated Transistors for Very High Frequency DC–DC Converters

This paper presents a method to optimize integrated lateral double-diffused MOSFET transistors for use in very high frequency (VHF, 30-300 MHz) dc-dc converters. A transistor model valid at VHF switching frequencies is developed. Device parameters are related to layout geometry and the resulting layout versus loss tradeoffs are illustrated. A method of finding an optimal layout for a given converter application is developed and experimentally verified in a 50-MHz converter, resulting in a 54% reduction in power loss over a hand-optimized device. It is further demonstrated that hot-carrier limits on device safe operating area may be relaxed under soft switching, yielding significant further loss reduction. A device fabricated with 3-μm gate length in 20-V design rules is validated at 35 V, offering reduced parasitic resistance and capacitance, as compared to the 5.5-μm device. Compared to the original design, loss is up to 75% lower in the example application.