Title :
High voltage ESD protection strategies for USB and PCI applications for 180nm/130nm/90nm CMOS technologies
Author :
Jahanzeb, A. ; Duvvury, C. ; Cline, R. ; Sterrantino, S. ; Kothamasu, S. ; Somayaji, A.
Author_Institution :
Texas Instrum., Dallas, TX, USA
Abstract :
A new substrate pump based cascoded NTNMOS (NMOS-Triggered-NMOS) structure or CNTNMOS is presented for protecting high voltage power supplies for deep submicron CMOS processes. Use of this novel approach of a cascoded circuit is also reported for 5 V fail-safe and 5 V tolerant signal operation with examples of application for USB and PCI high speed interface technologies in 180 nm, 130 nm and 90 nm CMOS processes. The circuit displays reliable immunity to conventional and signal latchup as well as robust HBM performance to a level well over 2 kV.
Keywords :
CMOS integrated circuits; electrostatic discharge; peripheral interfaces; CMOS technology; NMOS-triggered-NMOS structure; cascoded circuit; electrostatic discharge protection; size 130 nm; size 180 nm; size 90 nm; universal serial bus; voltage 5 V; CMOS process; CMOS technology; Circuits; Displays; Electrostatic discharge; Power supplies; Protection; Signal processing; Universal Serial Bus; Voltage;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 2006. EOS/ESD '06.
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-5853-7115-0
