Design and characterization of a multi-RC-triggered MOSFET-based power clamp for on-chip ESD protection

We present a novel multi-RC-triggered MOSFET-based power clamp with up to 70% trigger circuit area reduction and improved transient HBM, MM, and CDM ESD clamping performance. A three-stage RC-trigger circuit design gives a 300 ns self-shutdown time during power-up for mistrigger leakage current control and an improved mistrigger immunity down to 1 mus power-up rise time. TLP and HBM hardware characterization data from a 90 nm CMOS technology show >5A failure current and >3 kV HBM robustness for a designed MOSFET width of 4000 mum.