Title :
Design and characterization of a multi-RC-triggered MOSFET-based power clamp for on-chip ESD protection
Author :
Junjun Li ; Gauthier, R. ; Mitra, S. ; Putnam, C. ; Chatty, K. ; Halbach, R. ; Seguin, C.
Author_Institution :
Semicond. R&D Center, Syst. & Technol. Group, IBM, Essex Junction, VT, USA
Abstract :
We present a novel multi-RC-triggered MOSFET-based power clamp with up to 70% trigger circuit area reduction and improved transient HBM, MM, and CDM ESD clamping performance. A three-stage RC-trigger circuit design gives a 300 ns self-shutdown time during power-up for mistrigger leakage current control and an improved mistrigger immunity down to 1 mus power-up rise time. TLP and HBM hardware characterization data from a 90 nm CMOS technology show >5A failure current and >3 kV HBM robustness for a designed MOSFET width of 4000 mum.
Keywords :
CMOS integrated circuits; MOSFET; RC circuits; clamps; electrostatic discharge; CMOS technology; electrostatic discharge; mistrigger leakage current control; multiRC-triggered MOSFET design; on-chip ESD protection; power clamp; self-shutdown time; size 4000 mum; size 90 nm; time 300 ns; CMOS technology; Circuit synthesis; Clamps; Electrostatic discharge; Hardware; Leakage current; MOSFET circuits; Protection; Robustness; Trigger circuits;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 2006. EOS/ESD '06.
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-5853-7115-0
