DocumentCode
502596
Title
Comprehensive ESD protection for flip-chip products in a dual gate oxide 65nm CMOS technology
Author
Miller, J.W. ; Etherton, M. ; Khazhinsky, M.G. ; Stockinger, M. ; Weldon, J.C.
Author_Institution
Freescale Semicond. Inc., Austin, TX, USA
fYear
2006
fDate
10-15 Sept. 2006
Firstpage
186
Lastpage
195
Abstract
In this paper we present a modular and flexible new active MOSFET ESD rail clamp network configuration for use in flip-chip products. A key challenge was to efficiently fit all required ESD elements for an OVDD segment wholly into the I/O cells of that segment, without need for power/ground or spacer cells.
Keywords
CMOS integrated circuits; MOSFET; electrostatic discharge; flip-chip devices; ESD protection; I-O cell; MOSFET; OVDD segment; clamp network configuration; dual gate oxide CMOS technology; flip-chip product; size 65 nm; CMOS technology; Capacitors; Clamps; Diodes; Electrostatic discharge; Integrated circuit noise; MOSFET circuits; Protection; Rails; Trigger circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium, 2006. EOS/ESD '06.
Conference_Location
Anaheim, CA
Print_ISBN
978-1-5853-7115-0
Type
conf
Filename
5256782
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