• DocumentCode
    502613
  • Title

    Dual-direction Isolated NMOS-SCR device for system level ESD protection

  • Author

    Vashchenko, V.A. ; Hopper, P.J.

  • Author_Institution
    Nat. Semicond. Corp., Santa Clara, CA, USA
  • fYear
    2006
  • fDate
    10-15 Sept. 2006
  • Firstpage
    64
  • Lastpage
    68
  • Abstract
    A novel dual-direction device is suggested for system level ESD protection. The device combines both a deep NWELL isolated snapback NMOS and a lateral SCR structure using a shared regions approach. ESD pulse operation of the device has been experimentally studied for a 0.35 mum 5 V CMOS process by numerical simulation and then experimentally validated for system level IEC specification requirements.
  • Keywords
    CMOS analogue integrated circuits; MOS-controlled thyristors; electrostatic discharge; CMOS process; ESD pulse operation; IEC specification requirement; deep NWELL isolated snapback; dual-direction Isolated NMOS-SCR device; numerical simulation; size 0.35 mum; system level ESD protection; voltage 5 V; Anodes; Atherosclerosis; CMOS process; Cathodes; Electrostatic discharge; MOS devices; Protection; System-on-a-chip; Thyristors; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Overstress/Electrostatic Discharge Symposium, 2006. EOS/ESD '06.
  • Conference_Location
    Anaheim, CA
  • Print_ISBN
    978-1-5853-7115-0
  • Type

    conf

  • Filename
    5256800
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=502613