DocumentCode :
502614
Title :
Area-efficient, reduced and no-snapback PNP-based ESD protection in advanced Smart Power technology
Author :
Gendron, A. ; Salamero, C. ; Bafleur, M. ; Nolhier, N. ; Renaud, P. ; Besse, P.
Author_Institution :
Freescale Semicond., Toulouse, France
fYear :
2006
fDate :
10-15 Sept. 2006
Firstpage :
69
Lastpage :
76
Abstract :
A new approach, based on reduced and no-snapback components, was studied to face high-voltages I/Os severe ESD specifications. An accurate physical analysis of the mechanisms encountered during ESD stresses drove to define the parameters controlling the snapback and the high current RON, and then to quantify the attainable performances. For the first time in Smart Power technologies, design rules are drawn to take full advantage of self-biased PNP for efficient high voltages protections. TLP characterizations have confirmed the high potentialities of PNP.
Keywords :
electrostatic discharge; power integrated circuits; PNP-based ESD protection; Smart Power technologies; no-snapback components; reduced components; Automotive engineering; CMOS technology; Electrostatic discharge; Guidelines; Low voltage; Performance analysis; Power dissipation; Protection; Robustness; Stress control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 2006. EOS/ESD '06.
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-5853-7115-0
Type :
conf
Filename :
5256801
Link To Document :
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