Title :
Novel technique to reduce latch-up risk due to ESD protection devices in Smart Power technologies
Author :
Cerati, L. ; Cecchetto, L. ; Dissegna, M. ; Andreini, A. ; Ricotti, G.
Author_Institution :
STMicroelectronics, Agrate Brianza, Italy
Abstract :
N-well pockets connected to the cathode of ESD diodes may be source of parasitic electrons current in P-/P++ substrates. In this paper a methodology to reduce this latch-up risk is proposed. The electrical performances of this protection technique have been characterized and the results have been validated by device simulations.
Keywords :
electrostatic discharge; power bipolar transistors; semiconductor device breakdown; semiconductor device models; semiconductor diodes; ESD protection devices; N-well pockets; device simulations; latch-up risk reduction; parasitic NPN bipolar transistors; parasitic electrons current; smart power technologies; Bipolar transistors; Breakdown voltage; Cathodes; Diodes; Electrons; Electrostatic discharge; Power generation; Protection; Testing; Thyristors;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 2006. EOS/ESD '06.
Conference_Location :
Anaheim, CA
Print_ISBN :
978-1-5853-7115-0
