Turn-off characteristics of the CMOS snapback ESD protection devices - new insights and its implications

Author

Vashchenko, V.A. ; Scholz, M. ; Jansen, P. ; Petersen, R. ; Natarajan, M.I. ; Tremouilles, D. ; Sawada, M. ; Nakaei, T. ; Hasebe, T. ; Ter Beek, M. ; Groeseneken, G.

Author_Institution

Nat. Semicond., Santa Clara, CA, USA

fYear

2006

fDate

10-15 Sept. 2006

Firstpage

39

Lastpage

45

Abstract

The residual voltage across the ESD snapback protection device after its turn-off is one of the key parameters that must be considered for efficient ESD protection design. Turn-off characteristics of various snapback devices (5VNMOS, 5V LVTSCR and 12V DeMOS-SCR), are analyzed with experimental data for the first time and it is demonstrated that the residual voltage after turn-off is a unique parameter and depends on the type of ESD device, its architecture and layout. The residual voltage after turn-off can vary in a wide range from holding voltage to DC breakdown voltage and is a function of the ESD pulse amplitude. The underlying physical mechanism causing the waveform behavior is discussed in detail.

Keywords

CMOS integrated circuits; electrostatic discharge; integrated circuit layout; CMOS snapback ESD protection device; DC breakdown voltage; ESD pulse amplitude; residual voltage; turn-off characteristics; waveform behavior; Breakdown voltage; Circuits; Data analysis; EPROM; Electrostatic discharge; MOS devices; Protection; Pulse measurements; Residual stresses; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium, 2006. EOS/ESD '06.

Conference_Location

Anaheim, CA

Print_ISBN

978-1-5853-7115-0

Type

conf

Filename

5256805