System event triggered latch-up in IC chips: test issues and chip level protection design

A growing trend in the industry today is for IC manufacturers to provide components with protection against system level events. Such events may be system level ESD, surge/lightning tests, or any other system level tests that may apply a transient stress to IC pins. Recent studies show IC devices that pass regular DC latch-up testing can still be triggered to latch-up and lock-up modes by system level events. Providing components with built-in latch-up/lock-up immunity to system events requires both careful test methodology development and extra design effort. This paper discusses efforts to set up an IC level test environments for system events and IC level design efforts to enhance interface IC devices with latch-up immunity to system events.