Process influence on product CDM ESD sensitivity

Effective ESD protection circuit design has become challenging due to rapid advances in process technology. This study was launched to address those concerns and to look for the process windows that preserve CDM ESD robustness for given ESD protection designs in deep sub micron technologies. Experimental results for 0.18 µm integrated CPU´s together with process window effects on CDM robustness are presented and discussed. New fault models that assumed process and design dependent TDSB event in a parasitic NPN transistor are proposed to explain unexpected CDM sensitivity.