DocumentCode
502660
Title
Compact modeling of vertical ESD protection NPN transistors for RF circuits
Author
Joshi, Sopan ; Rosenbaum, Elyse
Author_Institution
Department of Electrical & Computer Engineering · University of Illinois at Urbana-Champaign, 1308 W. Main St., 61801, USA
fYear
2002
fDate
6-10 Oct. 2002
Firstpage
292
Lastpage
298
Abstract
We present an easy-to-use, simulator-independent compact model of a vertical npn transistor suitable for ESD circuit simulation. In addition to including high-current and breakdown effects, we also model accurately the small-signal off-state impedance of the device using s-parameter measurements, for inclusion in RF circuit simulations. Experimental results are provided for silicon and SiGe npn transistors.
Keywords
Circuit simulation; Computational modeling; Computer simulation; Electric breakdown; Electrostatic discharge; Hardware design languages; Impedance; Protection; Radio frequency; Virtual colonoscopy;
fLanguage
English
Publisher
ieee
Conference_Titel
2002 Electrical Overstress/Electrostatic Discharge Symposium, 2002. EOS/ESD '02.
Conference_Location
Charlotte, NC, USA
Print_ISBN
978-1-5853-7040-5
Electronic_ISBN
978-1-5853-7040-5
Type
conf
Filename
5267008
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