ESD protection by keep-on design for a 550 V fluorescent lamp control IC with integrated LDMOS power stage

A design is described where large output LDMOS transistors conduct the ESD current, utilizing the LDMOS drain-gate capacitance and the gate driver circuitry. Thus the need for separate ESD protections is eliminated. The method is demonstrated in a lamp ballast IC in a thin film SOI 650 V Smart Power technology. Circuit simulation is used to optimize the gate driver circuitry for ESD performance. The predicted behavior under ESD is verified with transmission line pulse testing.