DocumentCode :
502664
Title :
ESD protection by keep-on design for a 550 V fluorescent lamp control IC with integrated LDMOS power stage
Author :
van Zwol, J. ; van den Berg, A. ; Smedes, T.
Author_Institution :
Philips Semiconductors, Gerstweg 2, 6534 AE Nijmegen, the Netherlands
fYear :
2002
fDate :
6-10 Oct. 2002
Firstpage :
270
Lastpage :
276
Abstract :
A design is described where large output LDMOS transistors conduct the ESD current, utilizing the LDMOS drain-gate capacitance and the gate driver circuitry. Thus the need for separate ESD protections is eliminated. The method is demonstrated in a lamp ballast IC in a thin film SOI 650 V Smart Power technology. Circuit simulation is used to optimize the gate driver circuitry for ESD performance. The predicted behavior under ESD is verified with transmission line pulse testing.
Keywords :
Capacitance; Circuit simulation; Distributed parameter circuits; Driver circuits; Electronic ballasts; Electrostatic discharge; Fluorescent lamps; Power transmission lines; Protection; Thin film circuits;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
2002 Electrical Overstress/Electrostatic Discharge Symposium, 2002. EOS/ESD '02.
Conference_Location :
Charlotte, NC, USA
Print_ISBN :
978-1-5853-7040-5
Electronic_ISBN :
978-1-5853-7040-5
Type :
conf
Filename :
5267013
Link To Document :
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