DocumentCode
502673
Title
A study of high current characteristics of devices in a 0.13µm CMOS technology
Author
Tan, Pee-Ya ; Manna, Indrajit ; Tan, Yew-Chee ; Lo, Keng-Foo ; Li, Pian-Hong
Author_Institution
Chartered Semiconductor Mfg. Ltd., 60 Woodlands Industrial Park D St 2, Singapore 738406
fYear
2002
fDate
6-10 Oct. 2002
Firstpage
186
Lastpage
193
Abstract
This paper evaluates the high current performance of several devices in 0.13µm CMOS process as function of layout parameters using transmission line pulse (TLP) technique. Devices characterized include GGNMOS, PMOS, STI bounded diodes, Polysilicon bounded diodes, N+ contact, Cu metal line and via.
Keywords
CMOS process; CMOS technology; Circuit testing; Electric breakdown; Electrostatic discharge; Failure analysis; Fingers; Protection; Robustness; Semiconductor diodes;
fLanguage
English
Publisher
ieee
Conference_Titel
2002 Electrical Overstress/Electrostatic Discharge Symposium, 2002. EOS/ESD '02.
Conference_Location
Charlotte, NC, USA
Print_ISBN
978-1-5853-7040-5
Electronic_ISBN
978-1-5853-7040-5
Type
conf
Filename
5267022
Link To Document