ESD degradation analysis of poly-Si N-type TFT employing TLP (Transmission Line Pulser) test

Degradation mechanisms of poly-Si N-type TFT due to ESD stress are reported employing TLP (Transmission Line Pulser) test. ESD pulse generated by TLP is applied on the drain and the gate of poly-Si TFT. Experimental results show that degradations caused by ESD stress on the drain are classified into three different failure modes depending on the strength of ESD stress; degradation regime, partial failure regime and complete failure regime. ESD stress on the gate results in the shift of the threshold voltage (VTH), the decrease of on-current and the increase of off-current. ESD stress on the gate of poly-Si TFT increases the gate oxide fixed trap charge s, which is verified by C-V measurements.