DocumentCode
502685
Title
Technology CAD evaluation of BiCMOS protection structures operation including spatial thermal runaway
Author
Vashchenko, Vladislav ; Concannon, Ann ; Beek, Marcel Ter ; Hopper, Peter
Author_Institution
NSC, 2900 Semiconductor Drive, M/S E-155, Santa Clara, CA 95052-8090, USA
fYear
2002
fDate
6-10 Oct. 2002
Firstpage
101
Lastpage
110
Abstract
A 2-D simulation approach that takes into account the 3D effects of electro-thermal instability during ESD operation, is presented. The method is used to provide physical evaluation of a safe operation regime for BiCMOS ESD protection structures and circuits. ESD stress induced hot spot formation using 3D simulation has been presented for the case of a simplified snapback n-MOS device.
Keywords
BiCMOS integrated circuits; Protection;
fLanguage
English
Publisher
ieee
Conference_Titel
2002 Electrical Overstress/Electrostatic Discharge Symposium, 2002. EOS/ESD '02.
Conference_Location
Charlotte, NC, USA
Print_ISBN
978-1-5853-7040-5
Electronic_ISBN
978-1-5853-7040-5
Type
conf
Filename
5267035
Link To Document