DocumentCode :
502721
Title :
Research on dual-Processor sharing single DRAM
Author :
Gang, Zhang ; Bo, Zhang
Author_Institution :
Coll. of Inf. Eng., Taiyuan Univ. of Technol., Taiyuan, China
Volume :
2
fYear :
2009
fDate :
8-9 Aug. 2009
Firstpage :
532
Lastpage :
535
Abstract :
This paper presents a scheme of dual-port single memory controlling (DSMC) system based on switching, by which the dual-processor can access the shared single DDR SDRAM simultaneously and without collision. Therefore, the symmetric multi-processor (SMP) structure can utilize high-density, low-price DDR SDRAM as the shared memory to improve the system performance significantly. The DSMC system comprises of command interface module, data buffer module, logic arbiter module, quick data path module, DRAM command interface module, clock module and refresh module. The whole design is described in VHDL, and is verified with the FPGA in Xilinx EDK platform.
Keywords :
DRAM chips; field programmable gate arrays; hardware description languages; microprocessor chips; DDR SDRAM; DRAM command interface module; FPGA; VHDL; Xilinx EDK platform; clock module; data buffer module; dual-port single memory controlling system; dual-processor; logic arbiter module; quick data path module; refresh module; symmetric multi-processor; Communication system control; Computer buffers; Control systems; DRAM chips; Educational institutions; Field programmable gate arrays; Logic; Paper technology; Random access memory; SDRAM; SMP; based on swithcing; dual-port DDR controller; dual-processor;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computing, Communication, Control, and Management, 2009. CCCM 2009. ISECS International Colloquium on
Conference_Location :
Sanya
Print_ISBN :
978-1-4244-4247-8
Type :
conf
DOI :
10.1109/CCCM.2009.5267550
Filename :
5267550
Link To Document :
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