PMOSFET-based ESD protection in 65nm bulk CMOS technology for improved external latchup robustness

Author

Li, Junjun ; Gauthier, Robert ; Chatty, Kiran ; Kontos, Dimitrios ; Muhammad, Mujahid ; Woo, Min ; Putnam, Christopher ; Russ, Christian ; Alvarez, David ; Schneider, Jens ; Tan, Pee Ya

Author_Institution

IBM Semicond. R&D Center, Syst. & Technol. Group, Essex Junction, VT, USA

fYear

2005

fDate

8-16 Sept. 2005

Firstpage

1

Lastpage

8

Abstract

We present for the first time an ESD protection strategy using silicide-blocked PMOSFETs to improve negative-mode external latchup robustness by eliminating N+ junctions directly connected to the I/O pad. 100 ns TLP data of thin (T_ox=1.25 nm) and thick oxide (T_ox = 5.2 nm) silicide-blocked PMOSFETs in a 65 nm CMOS technology show failure currents of ~6 mA/mum and ~5 mA/mum respectively, suitable for on-chip ESD protection.

Keywords

CMOS integrated circuits; MOSFET; electrostatic discharge; radiation hardening (electronics); semiconductor junctions; I/O pad; N+ junction elimination; TLP data; bulk CMOS technology; failure currents; negative-mode external latchup robustness; on-chip PMOSFET-based ESD protection strategy; size 65 nm; thick oxide silicide-blocked PMOSFET; time 100 ns; CMOS technology; Circuit testing; Electrons; Electrostatic discharge; Inverters; MOSFET circuits; Protection; Research and development; Robustness; Semiconductor diodes;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Overstress/Electrostatic Discharge Symposium, 2005. EOS/ESD '05.

Conference_Location

Tucson, AZ

Print_ISBN

978-1-58537-069-6

Electronic_ISBN

978-1-58537-069-6

Type

conf

Filename

5271717