A PNP-triggered SCR with improved trigger techniques for high-speed I/O ESD protection in deep sub-micron CMOS LSIs

A PNP-triggered SCR with improved trigger techniques is proposed for high-speed I/O ESD protection. By using these techniques, a high trigger voltage, V_TRIG, for latch-up immunity during normal operating conditions, together with a low trigger voltage, Vt1, during ESD stress conditions, can be realized with simple design. Moreover, I/O circuits including the ESD protection are operable at a higher voltage than an on-chip core V_DD. The PNP-triggered SCR is demonstrated in our 90 nm CMOS technology, suitable trigger voltages at both conditions (V_TRIG = 4.0 V@125degC/ Vt1 = 2.0 V), and good ESD performances (HBM: 3500 V/ MM: 200 V) are achieved.