DocumentCode :
503016
Title :
Verification of CDM circuit simulation using an ESD evaluation circuit
Author :
Etherton, M. ; Willemen, J. ; Wilkening, W. ; Qu, N. ; Mettler, S. ; Fichtner, W.
Author_Institution :
Robert Bosch GmbH, Reutlingen, Germany
fYear :
2005
fDate :
8-16 Sept. 2005
Firstpage :
1
Lastpage :
10
Abstract :
In this work, the capability of circuit simulation to predict CDM robustness of integrated circuits and to determine weak circuit elements is studied. The applicability is demonstrated for an ESD evaluation circuit designed to enable the analysis and optimization of ESD protection strategies in an early design phase during the introduction of a new technology. CDM circuit simulation is compared to the measurement results of variations of this circuit in two different package types. Failure locations are verified with physical failure analysis.
Keywords :
electrostatic discharge; fault location; integrated circuit reliability; ESD evaluation circuit; ESD protection strategy; charged device model circuit simulation verification; failure location; integrated circuit; physical failure analysis; reliability; weak circuit element; Circuit simulation; Circuit testing; Design optimization; Electrostatic discharge; Failure analysis; Fault location; Integrated circuit technology; Packaging; Protection; Robustness;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 2005. EOS/ESD '05.
Conference_Location :
Tucson, AZ
Print_ISBN :
978-1-58537-069-6
Electronic_ISBN :
978-1-58537-069-6
Type :
conf
Filename :
5271815
Link To Document :
بازگشت