DocumentCode
503017
Title
Design automation to suppress cable discharge event (CDE) induced latchup in 90nm CMOS ASICs
Author
Brennan, Ciaran J. ; Chatty, Kiran ; Sloan, Jeff ; Dunn, Paul ; Muhammad, Mujahid ; Gauthier, Robert
Author_Institution
IBM Microelectron., Essex Junction, VT, USA
fYear
2005
fDate
8-16 Sept. 2005
Firstpage
1
Lastpage
5
Abstract
Design automation tools have been developed to suppress CDE-induced latchup in CMOS ASICs. The tools govern the placement of I/Os and cores subject to CDE and automate the insertion of well and substrate contacts with varying periodicities around CDE susceptible cells according to rules derived from an analytical latchup model.
Keywords
CMOS integrated circuits; application specific integrated circuits; electronic design automation; integrated circuit modelling; CDE-induced latchup; CMOS ASIC; analytical latchup model; cable discharge event induced latchup; design automation tools; size 90 nm; substrate contacts; CMOS integrated circuits; Cables; Circuit testing; Contact resistance; Design automation; Electrons; Electrostatic discharge; Equations; Microelectronics; Rivers;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Overstress/Electrostatic Discharge Symposium, 2005. EOS/ESD '05.
Conference_Location
Tucson, AZ
Print_ISBN
978-1-58537-069-6
Electronic_ISBN
978-1-58537-069-6
Type
conf
Filename
5271816
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