Title :
The influence of implanted sub-collector on CMOS latchup robustness
Author :
Voldman, Steven H. ; Gebreselasie, Ephrem G.
Author_Institution :
IBM Microelectron., Essex Junction, VT, USA
Abstract :
This paper discusses the integration of sub-collector implants into a dual-well CMOS for improvement in CMOS latchup robustness. Experimental work demonstrates CMOS latchup tradeoffs exist between the enhancement of the npn bipolar current gain, betanpn and reduction of the pnp bipolar current gain, betapnp. Additionally, the integration of sub-collectors, as well as trench isolation (TI) and deep trench (DT) isolation structures into CMOS dual-well structures will be highlighted.
Keywords :
CMOS integrated circuits; isolation technology; CMOS dual-well structures; CMOS latchup robustness; deep trench isolation; dual-well CMOS; implanted subcollector; npn bipolar current gain; pnp bipolar current gain; subcollector implants integration; BiCMOS integrated circuits; CMOS technology; Electrostatic discharge; Implants; Isolation technology; MOSFET circuits; Microelectronics; Robustness; Telephony; Testing;
Conference_Titel :
Electrical Overstress/Electrostatic Discharge Symposium, 2005. EOS/ESD '05.
Conference_Location :
Tucson, AZ
Print_ISBN :
978-1-58537-069-6
Electronic_ISBN :
978-1-58537-069-6
