The influence of implanted sub-collector on CMOS latchup robustness

This paper discusses the integration of sub-collector implants into a dual-well CMOS for improvement in CMOS latchup robustness. Experimental work demonstrates CMOS latchup tradeoffs exist between the enhancement of the npn bipolar current gain, beta_npn and reduction of the pnp bipolar current gain, beta_pnp. Additionally, the integration of sub-collectors, as well as trench isolation (TI) and deep trench (DT) isolation structures into CMOS dual-well structures will be highlighted.