Impact of elevated source drain architecture on ESD protection devices for a 90nm CMOS technology node

The electro-static discharge robustness of different elevated source drain architectures on a 90 nm CMOS technology is investigated. The study is performed on poly isolated diodes and grounded gate NMOS using transmission line pulse and human body model testing methods. It is found that an improvement up to 45% in ESD robustness can be obtained by the use of elevated source drain process option. Failure analysis and qualitative device simulation have been performed to obtain better understanding and interpret the measurement results.