• DocumentCode
    503071
  • Title

    Impact of layer thickness variations of SOI-wafer on ESD-robustness

  • Author

    Graf, M. ; Bychikhin, S. ; Dietz, F. ; Dudek, V. ; Pogany, D. ; Gornik, E. ; Soppa, W. ; Wolf, H.

  • Author_Institution
    Atmel, Heilbronn, Germany
  • fYear
    2003
  • fDate
    21-25 Sept. 2003
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    For a Smart-Power-Technology on SOI new concepts for suitable ESD protection elements are investigated. It is shown that variations of the maximum failure current correlate with undue thickness variations of the active silicon layer whereas the DC-characteristics in the low current regime are not influenced.
  • Keywords
    electrostatic discharge; power integrated circuits; silicon-on-insulator; ESD protection; SOI-wafer; Smart-Power-Technology; layer thickness variations; Anodes; Boundary conditions; Cathodes; Circuits; Electrostatic discharge; Electrostatic interference; Protection; System testing; Variable speed drives; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electrical Overstress/Electrostatic Discharge Symposium, 2003. EOS/ESD '03.
  • Conference_Location
    Las Vegas, NB
  • Print_ISBN
    978-1-5853-7057-3
  • Electronic_ISBN
    978-1-5853-7057-3
  • Type

    conf

  • Filename
    5272034
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=503071