High performance IC package design and electrical reliability

Many changes have occurred in packaging technology during the last five years as a result of a continuous drive to higher electrical performance and higher I/O count chips. In meeting these performance demands, the complexity of the packages has increased which in turn has led to an increased susceptibility to electrostatic discharge (ESD) events. This paper will review the current packaging field, discuss future trends in IC packaging, and relate packaging design considerations such as trace spacing and material selection to the ESD performance of IC packages.