A study on high-density high-speed SerDes design in buildup flip chip ball grid array packages

A study on high-density high-speed SerDes (HHS) designs in buildup laminate flip chip ball grid array (fcBGA) packages is presented in this paper. Experiences have shown that three main capacitive discontinuities happen in flip chip bump area, core PTH via area and BGA transition area. Literature [1] have studied three PTH via configurations for differential pairs and suggested that a routing structure with PTH via on the top of BGA be the best design option, which implies that all Serdes routings have to be done in buildup layers above the core layer. However, with growing Serdes number, limited buildup layer number and specified X-talk number, one cannot route all Serdes differential pairs in the buildup layers above the core layer. In a result, routing some Serdes differential pairs in buildup layers below the core becomes a must. In our paper, the three PTH via structures in [1] are analyzed in detail. In order to obtain a more realistic electrical performance, we include die bump, package wiring and BGA transition with a small portion of PCB transmission line in our models. Ansoft full-wave HFSS tool is used to run for S-parameters. Measurement data from a test system were used to guarantee the correctness of our model setup including boundary condition, port and material definitions and so on. Our studies have shown that all three PTH via configurations can be optimized and provide a similar level electrical performances up to 15 GHz, which means a smaller buildup layer number and a package cost reduction for a given application. Numerical results for a 4-4-4 buildup package optimization are presented to show the merit of our methodology.